Method of fabricating semiconductor device and semiconductor device

ABSTRACT

A method of fabricating a semiconductor device according to an embodiment includes forming a first pattern having linear parts of a constant line width and a second pattern on a foundation layer, the second pattern including parts close to the linear parts of the first pattern and parts away from the linear parts of the first pattern and constituting closed loop shapes independently of the first pattern or in a state of being connected to the first pattern and carrying out a closed loop cut at the parts of the second pattern away from the linear parts of the first pattern.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a reissue of U.S. Pat. No. 8,183,148, issued on May22, 2012 from U.S. patent application Ser. No. 12/542,540 filed Aug. 17,2009, which is based upon and claims the benefit of priority from priorJapanese Patent Application No. 2008-209849, filed on Aug. 18, 2008, theentire contents of both of which are incorporated herein by reference.

BACKGROUND

Recently, in accordance with miniaturization of a semiconductor element,a method capable of forming a pattern having a dimension beyond aresolution limit in lithography method is required.

As one sample of the method, a method is known, that includes steps offorming sidewall patterns on side surfaces of core materials,eliminating the core materials, and etching a workpiece film by usingthe sidewall patterns as a mask, for example, disclosed inJP-A-1996-55908.

Since the sidewall patterns and wiring patterns formed by using thesidewall patterns as a mask have closed loop shapes, a step of a closedloop cut for cutting a part of the closed loop shape is needed. In casethat the other patterns exist close to the sites where the closed loopcut is carried out, generally, spaces are created between the otherpatterns in terms of a margin of displacement at the alignment in thelithography method.

BRIEF SUMMARY

A method of fabricating a semiconductor device according to anembodiment includes forming a first pattern having linear parts of aconstant line width and a second pattern on a foundation layer, thesecond pattern including parts close to the linear parts of the firstpattern and parts away from the linear parts of the first pattern andconstituting closed loop shapes independently of the first pattern or ina state of being connected to the first pattern and carrying out aclosed loop cut at the parts of the second pattern away from the linearparts of the first pattern.

A method of fabricating a semiconductor device according to anotherembodiment includes forming a first pattern having linear parts of aconstant line width and a second pattern having parts parallel to thefirst pattern which have a first distance between the linear parts ofthe first pattern, and constituting closed loop shapes independently ofthe first pattern or in a state of being connected to the first patternand forming a resist in the parts of the second pattern so as to have asecond distance between the linear parts of the first pattern largerthan the first distance, and carrying out a closed loop cut at the partsof the second pattern in which the resist is formed.

A method of fabricating a semiconductor device according to anotherembodiment includes forming a first pattern group including a pluralityof first patterns arranged at a predetermined pitch, and second patterngroup including a plurality of second patterns arranged at thepredetermined pitch, the closest second patterns to at least the firstpattern group of the plural second patterns having parallel partsparallel to the first pattern group and parts away from the secondpattern group and constituting closed loop shapes independently of thefirst pattern group or in a state of being connected to the firstpattern group and carrying out a closed loop cut at the parts of thesecond pattern away from the first pattern group.

A semiconductor device according to another embodiment includes a firstpattern group including a plurality of first patterns arranged at apredetermined pitch and a second pattern group including a plurality ofsecond patterns arranged at the predetermined pitch, wherein the closestsecond patterns to at least the first pattern group of the plural secondpatterns have parallel parts parallel to the first pattern group andnon-parallel parts formed so as to be connected to the parallel parts,to be away from the first pattern group and to be not parallel to thefirst pattern group.

BRIEF DESCRIPTION OF THE DRAWING

FIGS. 1A to 1H are cross-sectional views schematically showing eachfeature in a fabrication process of a semiconductor device according toa first embodiment;

FIGS. 2A to 2C are plan views schematically showing processes of aclosed loop cut carried out between the process shown in FIG. 1D and theprocess shown in FIG. 1E;

FIGS. 3A to 3H are cross-sectional views schematically showing eachfeature in a fabrication process of a semiconductor device according toa second embodiment;

FIGS. 4A to 4C are plan views schematically showing processes of aclosed loop cut carried out after the process shown in FIG. 3H;

FIG. 5A is a plan view schematically showing an example of side wallpatterns used in a third embodiment;

FIG. 5B is a detail view of an “A” part of the side wall patterns shownin FIG. 5A;

FIG. 6A is a plan view schematically showing a structure of a wiringpattern in a wiring layer of a phase-change memory used in a fourthembodiment;

FIG. 6B is a detail view of a “B” part of the side wall patterns shownin FIG. 6A;

FIGS. 7A to 7F are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a fourth embodiment;

FIGS. 8A to 8C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a fifth embodiment;

FIGS. 9A to 9C are main part plan views schematically showing each mainpart of upper wiring layers used in an example of a fabrication processaccording to a sixth embodiment;

FIGS. 10A to 10C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a seventh embodiment;

FIGS. 11A to 11C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to an eighth embodiment;

FIGS. 12A to 12C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a ninth embodiment;

FIGS. 13A to 13C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a tenth embodiment;

FIGS. 14A to 14C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to an eleventh embodiment;

FIGS. 15A to 15C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a twelfth embodiment;

FIGS. 16A to 16C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a thirteenth embodiment;

FIGS. 17A to 17H are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a fourteenth embodiment;

FIGS. 18A to 18C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a fifteenth embodiment;

FIGS. 19A to 19C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a sixteenth embodiment;

FIGS. 20A to 20C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a seventeenth embodiment;

FIGS. 21A to 21C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to an eighteenth embodiment;

FIGS. 22A to 22C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a nineteenth embodiment;

FIGS. 23A to 24C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a twentieth embodiment;

FIGS. 24A to 24C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a twenty-first embodiment; and

FIGS. 25A to 25C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a twenty-second embodiment.

DETAILED DESCRIPTION

A method of fabricating a semiconductor device according to theembodiment includes forming a first pattern having linear parts of aconstant line width and a second pattern on a foundation layer, thesecond pattern including parts close to the linear parts of the firstpattern and parts away from the linear parts of the first pattern andconstituting closed loop shapes independently of the first pattern or ina state of being connected to the first pattern and carrying out aclosed loop cut at the parts of the second pattern away from the linearparts of the first pattern.

As the foundation layer, a substrate such as a silicon substrate or aworkpiece film to be processed by using the first and second patterns asa mask can be used. Further, the workpiece film can be formed betweenthe foundation layer and the first and second patterns.

As the first and second patterns, a bit-line and a word lineconstituting a memory device, a wiring by a line and space, or a patternused as a mask can be used.

As the first pattern, for example, a pattern having a closed loop shapeor a line pattern can be used. Further, the first pattern can include apart having a line width wider than that of the linear part of theconstant line width.

The part of the second pattern close to the linear part of the firstpattern is, for example, a parallel part close to and parallel to thelinear part of the first pattern. The parallel part of the secondpattern can have a linear shape or a carved shape, if it is parallel tothe linear part of the first pattern.

(First Embodiment)

FIGS. 1A to 1H are cross-sectional views schematically showing eachfeature in a fabrication process of a semiconductor device according tothe first embodiment. FIGS. 2A to 2C are plan views schematicallyshowing processes of a closed loop cut carried out between the processshown in FIG. 1D and the process shown in FIG. 1E.

As shown in FIG. 1A, a wiring material (a workpiece film) 11 for forminga wiring layer via a foundation layer 10 is formed on a semiconductorsubstrate such as a silicon substrate, a mask material 12 is formed onthe wiring material 11 and core patterns 13a, 13b are formed on the maskmaterial 12 by a lithography method and an etching process which use aresist. The core patterns 13a, 13b have, for example, a line width (forexample, 40 nm) near the resolution limit “W” of lithography method.

As the wiring material 11, for example, Cu, W, Al or the like can beused. As the mask material 12, for example, silicon oxide film or thelike can be used. As the core patterns 13a, 13b, for example, amorphoussilicon film or the like can be used.

Next, as shown in FIG. 1B, a slimming treatment is carried out so as tomake the width of the core patterns 13a, 13b thin up to a half size byan anisotropic etching or the like. By this, the core patterns 13a, 13bhaving a line width (for example, 20 nm) of almost a half size of theresolution limit “W” can be obtained.

Next, as shown in FIG. 1C, a film to become a material of side wallpatterns is deposited on the whole surfaces including the side surfacesof the core patterns 13a, 13b after the slimming treatment, parts of thefilm which are deposited on the upper surfaces of the core patterns 13a,13b and the surface of the mask material 12 are eliminated by using theanisotropic etching or the like so as to form side wall patterns 14a,14b on the side surfaces of the core patterns 13a, 13b. The side wallpatterns 14a, 14b has, for example, a line width and an distance ofalmost a half size of the resolution limit “W”.

The side wall patterns 14a, 14b are formed of a material having a highetching selectivity to the core patterns 13a, 13b, for example, if thecore patterns 13a, 13b are formed of the amorphous silicon film, siliconnitride film or the like can be used as the material.

Next, as shown in FIG. 1D, the core patterns 13a, 13b are eliminated bya dry etching such as a chemical dry etching (CDE), a reactive ionetching (RIE) or the like so as to leave the side wall patterns 14a, 14bhaving a high etching selectivity to the core patterns 13a, 13b. At thistime, each of the both end portions of the side wall patterns 14a, 14bforms a closed loop shape.

In FIG. 2A, the side wall patterns 14b show an object pattern (thesecond pattern) which is an object of the closed loop cut, and the sidewall patterns 14a show an adjacency pattern (the first pattern) adjacentto the side wall patterns 14b. In case of the embodiment, the side wallpatterns 14a, 14b include linear parts of a constant line width.Further, the adjacency pattern can be an object of the closed loop cut.In order to carry out the closed loop cut of the side wall patterns 14b,in terms of a margin of displacement at the alignment in the lithographymethod, it is needed for a region of the side wall patterns 14b wherethe closed loop cut is carried out to be away from the side wallpatterns 14a so that the resist 15 does not fall over the side wallpatterns 14a. Therefore, the side wall patterns 14b are formed so as tohave the following shape.

Namely, the side wall patterns 14b are close to the side wall patterns14a so as to have a distance “d” (a first distance) between the sidewall patterns 14a, and has parallel parts 140 parallel to the side wallpatterns 14a and nonparallel parts 141 formed so as to be connected tothe parallel parts 140 and to be not parallel to the side wall patterns14a, and cut regions 141a where the closed loop cut is carried out isformed in the nonparallel parts 141. The nonparallel parts 141 areformed in a shape bent in an oblique direction from the joining point ofthe parallel part 140 and the nonparallel part 141 so as to be apartfrom the side wall patterns 14a, but it can have a shape bent in arectangular direction.

As shown in FIG. 2B, a space “S” (a second distance) is formed on thecut region 141a located at the end portions of the side wall patterns14b, between the side wall patterns 14a and a resist 15 is formed, andas shown in FIG. 2C, the cut region 141a of the side wall patterns 14bis cut by the lithography method. The space “S” is formed so as to belarger than the distance “d” (the first distance) between the side wallpatterns 14a and the side wall patterns 14b.

Next, as shown in FIG. 1E, the mask material 12 is eliminated by usingthe side wall patterns 14a, 14b as a mask and by a dry etching or thelike where a gas such as CF₄, CHF₃ is used so as to form mask patterns12a, 12b, and as shown in FIG. 1F, the side wall patterns 14a, 14b areeliminated by a wet etching or the like.

Next, as shown in FIG. 1G, the wiring material 11 is etched by using themask patterns 12a, 12b so as to form wiring patterns 11a, 11b, and asshown in FIG. 1H, the mask patterns 12a, 12b are eliminated by the wetetching or the like.

According to the first embodiment, even if the side wall patterns havean arrangement pitch less than the resolution limit “W” in lithographymethod, the closed loop cut of the side wall patterns can be carriedout.

(Second Embodiment)

FIGS. 3A to 3H are cross-sectional views schematically showing eachfeature in a fabrication process of a semiconductor device according tothe second embodiment and FIGS. 4A to 4C are plan views schematicallyshowing processes of a closed loop cut carried out after the processshown in FIG. 3H. In the first embodiment, the wiring material ispreliminarily formed, the closed loop cut of the end portions of theside wall patterns are carried out, and then the wiring pattern isformed from the wiring material, but in the second embodiment, thewiring pattern having a closed loop shape is formed, and then the closedloop cut of the end portions of the side wall patterns is carried out.

As shown in FIG. 3A, the mask material 12 is formed on a semiconductorsubstrate such as a silicon substrate via the foundation layer 10, andthe core patterns 13a, 13b are formed on the mask material 12 by alithography method and an etching process which use a resist. The corepatterns 13a, 13b have, for example, a line width (for example, 40 nm)near the resolution limit “W” of lithography method.

As the mask material 12, for example, silicon oxide film or the like canbe used. As the core patterns 13a, 13b, for example, amorphous siliconfilm or the like can be used.

Next, as shown in FIG. 3B, a slimming treatment is carried out so as tomake the width of the core patterns 13a, 13b thin up to a half size byan anisotropic etching or the like. By this, the core patterns 13a, 13bhaving a line width (for example, 20 nm) of almost a half size of theresolution limit “W” can be obtained.

Next, as shown in FIG. 3C, a film to become a material of side wallpatterns is deposited on the whole surfaces including the side surfacesof the core patterns 13a, 13b after the slimming treatment, parts of thefilm which are deposited on the upper surfaces of the core patterns 13a,13b and the surface of the mask material 12 are eliminated by using theanisotropic etching or the like so as to form side wall patterns 14a,14b on the side surfaces of the core patterns 13a, 13b. The side wallpatterns 14a, 14b has, for example, a line width and an distance ofalmost a half size of the resolution limit “W”.

Next, as shown in FIG. 3D, the core patterns 13a, 13b are eliminated bya dry etching such as CDE, RIE or the like so as to leave the side wallpatterns 14a, 14b having a high etching selectivity to the core patterns13a, 13b. Each of the both end portions of the side wall patterns 14a,14b forms a closed loop shape similarly to the first embodiment.

Next, as shown in FIG. 3E, the mask material 12 is eliminated by usingthe side wall patterns 14a, 14b as a mask and by a dry etching or thelike where a gas such as CF₄, CHF₃ is used so as to form mask patterns12a, 12b, and as shown in FIG. 3F, the side wall patterns 14a, 14b areeliminated by a wet etching or the like.

Next, as shown in FIG. 3G, the wiring material 11 is formed on the wholesurfaces including grooves between the mask patterns 12a, 12b by asputtering method, a plating method or the like, and then the wiringmaterial 11 located outside the grooves is eliminated by a chemicalmechanical polishing (CMP) so as to fill the wiring material 11 in thegrooves between the mask patterns 12a, 12b. As the wiring material 11,for example, Cu, W, Al or the like can be used.

Next, as shown in FIG. 3H, the mask patterns 12a, 12b are eliminated soas to form the wiring patterns 11a, 11b and wide patterns 11e having awidth wider than that of the wiring patterns 11a, 11b. Both of the endportions of the wiring patterns 11a, 11b are formed in a closed loopshape.

In FIG. 4A, the wiring pattern 11b shows an object pattern (the secondpattern) which is an object of the closed loop cut, and the wiringpattern 11a shows an adjacency pattern (the first pattern) adjacent tothe wiring pattern 11b. In case of the embodiment, the wiring patterns11a, 11b include linear parts of a constant line width. Further, theadjacency pattern can be an object of the closed loop cut. In order tocarry out the closed loop cut of the wiring pattern 11b, in terms of amargin of displacement at the alignment in the lithography method, it isneeded for a region of the wiring pattern 11b where the closed loop cutis carried out to be away from the wiring pattern 11a so that the resist15 does not fall over the wiring pattern 11a. Therefore, the wiringpattern 11b is formed so as to have the following shape.

Namely, the wiring pattern 11b has parallel parts 110 parallel to thewiring pattern 11a and nonparallel parts 111 formed so as to beconnected to the parallel parts 110 and to be not parallel to the wiringpattern 11a, and cut regions 111a where the closed loop cut is carriedout is formed in the nonparallel parts 111. The nonparallel parts 111are formed in a shape bent in an oblique direction from the joiningpoint of the parallel part 110 and the nonparallel part 111 so as to beapart from the wiring pattern 11a, but it can have a shape bent in arectangular direction.

As shown in FIG. 4B, a space “S” (the second distance) is formed on thecut region 111a located at the end portion of the wiring pattern 11b,between the wiring pattern 11a and a resist 15 is formed, and as shownin FIG. 4C, the cut region 111a of the wiring pattern 11b is cut by thelithography method. The space “S” is formed so as to be larger than thedistance “d” (the first distance) between the wiring pattern 11a and thewiring pattern 11b.

According to the second embodiment, even if the wiring pattern has anarrangement pitch less than the resolution limit “W” in lithographymethod, the closed loop cut of the wiring pattern can be carried out.The side wall patterns 14b as the second pattern are close to the sidewall patterns 14a so as to have a distance “d” (a first distance)between the side wall patterns 14a, and has parallel parts 140 parallelto the side wall patterns 14a and nonparallel parts 141 formed so as tobe connected to the parallel parts 140 and to be not parallel to theside wall patterns 14a, and cut regions 141a where the closed loop cutis carried out is formed in the nonparallel parts 141.

(Third Embodiment)

FIG. 5A is a plan view schematically showing an example of side wallpatterns used in a third embodiment and FIG. 5B is a detail view of an“A” part of the side wall patterns shown in FIG. 5A. In the firstembodiment, the side wall patterns 14a as the first pattern have alinear shape and the side wall patterns 14b as the second pattern have anonlinear and bent shape, but in the third embodiment, the side wallpatterns 14a as the first pattern have a bent shape, and the side wallpatterns 14b as the second pattern have a linear shape and have the cutregions 141a in the end portions where the closed loop cut is carriedout.

According to the third embodiment, similarly to the first embodiment,even if the side wall patterns have an arrangement pitch less than theresolution limit “W” in lithography method, the closed loop cut of theside wall patterns can be carried out.

Next, the fourth to the eighth embodiments where the semiconductordevice of the first embodiment is applied to a phase-change memory willbe explained. The fourth to the eighth embodiments show a case that thewiring patterns 11a, 11b constituting each of wiring pattern groups 20A,20B include thirty-six (36) lines of 20 nm in line width respectively.

(Fourth Embodiment)

FIG. 6A is a plan view schematically showing a structure of a wiringpattern in a wiring layer of a phase-change memory used in a fourthembodiment and FIG. 6B is a detail view of a “B” part of the side wallpatterns shown in FIG. 6A.

As shown in FIG. 6A, the phase-change memory 1 includes a memory cellregion 2, a WL extraction region 3 where word lines (WL) are extracted,formed on the right and left sides of memory cell region 2, a BLextraction region 4 where bit lines (BL) are extracted, formed on thetop and bottom sides of memory cell region 2, and a peripheral circuitdisposed under the memory cell region 2.

The phase-change memory 1 includes a plurality of bit lines formed ofthe wiring patterns 11a, 11b extending in an “x” direction, a pluralityof word lines formed of the wiring patterns 21a, 21b extending in an “y”direction, and a plurality of memory cells disposed in each of crossingparts of the bit lines and the word lines. The memory cell includes aseries circuit having a variable resistive element formed ofchalcogenide or the like and a diode such as a Schottky diode. In thephase-change memory 1, signal lines for sell selection can be omitted sothat high cell-integration can be achieved.

A three dimensional memory structure can be configured by that a cellarray is configured so as to include a lower wiring layer where aplurality of word lines are formed, a memory layer having a plurality ofmemory cells and formed on the lower wiring layer, and an upper wiringlayer formed on the memory cells, where a plurality of bit lines areformed, and a plurality of the cell arrays are disposed on a siliconsubstrate in a stacked state.

As shown in FIG. 6A, the bit lines constituting the upper wiring layerinclude a first wiring pattern group 20A formed at a location totallyshifted in the right side and including the wiring pattern 11a (thefirst pattern) of a predetermined lines, and a second wiring patterngroup 20B formed at a location totally shifted in the left side andincluding the wiring pattern 11b (the second pattern) of a predeterminedlines.

As shown in FIG. 6A, the word lines constituting the lower wiring layerinclude a first wiring pattern group 20C formed at a location totallyshifted in the top side and including the wiring pattern 21a (the firstpattern) of a predetermined lines, and a second wiring pattern group 20Dformed at a location totally shifted in the bottom side and includingthe wiring pattern 21b (the second pattern) of a predetermined lines.

The wiring patterns 11a, 11b include terminals 11c to which the closedloop cut is carried out in one end portion, and contact fringes 11dformed in another end portion by that the closed loop cut is carried outafter a treatment of leaving the core materials is conducted. Theterminals 11c and the contact fringes 11d are formed in the WLextraction region 3. The wiring patterns 21a, 21b include terminals 21cto which the closed loop cut is carried out in one end portion, andcontact fringes 21d formed in another end portion by that the closedloop cut is carried out after a treatment of leaving the core materialsis conducted. The terminals 21c and the contact fringes 21d are formedin the BL extraction region 4.

As shown in FIG. 6B, in the wiring pattern 11b constituting the secondwiring pattern group 20B of the upper wiring layer, a plurality ofwiring patterns 11b adjacent to the first wiring pattern group 20Ainclude a parallel part 110 and a nonparallel part 111, and a pluralityof wiring patterns 11b located at a center portion do not have thenonparallel part 111. The first wiring pattern group 20A has also thesame structure, and the first and second wiring pattern groups 20C, 20Don the lower wiring layer have also the same structure.

FIGS. 7A to 7F are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the fourth embodiment. FIGS. 7A to 7D correspond to FIGS.1A to 1D respectively, FIG. 7E corresponds to FIG. 2B and FIG. 7Fcorresponds to FIG. 1H.

Similarly to the first embodiment, after the wiring material and themask material are formed on the foundation layer, as shown in FIG. 7A,the core patterns 13a, 13b are formed on the mask material. A pluralityof core patterns 13b of the second wiring pattern group 20B adjacent tothe first wiring pattern group 20A are bent in the end portions thereofin an oblique direction so as to be apart from the first wiring patterngroup 20A.

Next, as shown in FIG. 7B, a slimming treatment of the core patterns13a, 13b is carried out, and as shown in FIG. 7C, the side wall patterns14a, 14b are formed on the side surfaces of core patterns 13a, 13b afterthe slimming treatment, and as shown in FIG. 7D, the core patterns 13a,13b are eliminated by an etching so as to leave the side wall patterns14a, 14b.

As shown in FIG. 7E, a space “S” is formed on the cut region located atthe end portion of the side wall patterns 14b, between the first wiringpattern group 20A, and the resist 15 having a hexagonal shape is formed,and the cut regions of the side wall patterns 14b are cut by thelithography method. The space “S” between the first wiring pattern group20A and the resist 15 is, for example, set to 140 nm, in terms of amargin of displacement at the alignment in the lithography method.

Next, the mask material is eliminated by using the side wall patterns14a, 14b as a mask and by an etching so as to form mask patterns, andthe side wall patterns 14a, 14b are eliminated. Next, the wiringmaterial is etched by using the mask patterns so as to form wiringpatterns 11a, 11b, and the mask patterns are eliminated. As shown inFIG. 7F, the wiring patterns 11a, 11b having a line width and distanceof 20 nm are obtained.

According to the fourth embodiment, even if the side wall patterns havean arrangement pitch less than the resolution limit “W” in lithographymethod, the closed loop cut of the side wall patterns can be carriedout. Further, the first and second wiring pattern groups are alternatelyshifted in the right and left sides, and the top and bottom sides sothat the areas of the extraction regions 3, 4 can be reduced, and highcell-integration of the phase-change memory can be achieved.

(Fifth Embodiment)

FIGS. 8A to 8C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the fifth embodiment. FIG. 8A corresponds to FIG. 1D, FIG.8B corresponds to FIG. 2B, and FIG. 8C corresponds to FIG. 1H. Further,drawings corresponding to FIGS. 1A to 1C are omitted.

As shown in FIG. 8A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the fifth embodiment, the side wallpatterns 14b closest to the first wiring pattern groups 20A areconnected each other so as to form a closed loop shape and the otherthirty-four (34) lines of the side wall patterns 14b form the closedloop shapes between the side wall patterns 14b adjacent to each other.

After that, as shown in FIG. 8B, a space “S” is formed on the cut regionlocated at the end portions of the side wall patterns 14b, between thefirst wiring pattern group 20A, the resist 15 having a hexagonal shapeis formed, the cut region of the side wall patterns 14b is cut by thelithography method, and as shown in FIG. 8C, the wiring patterns 11a,11b similar to those of the fourth embodiment are formed.

(Sixth Embodiment)

FIGS. 9A to 9C are main part plan views schematically showing each mainpart of upper wiring layers used in an example of a fabrication processaccording to the sixth embodiment. FIG. 9A corresponds to FIG. 1D, FIG.9B corresponds to FIG. 2B, and FIG. 9C corresponds to FIG. 1H. Further,drawings corresponding to FIGS. 1A to 1C are omitted.

As shown in FIG. 9A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the sixth embodiment, the side wallpatterns 14b closest to the first wiring pattern groups 20A areconnected each other along the end portions of the other side wallpatterns 14b so as to form a closed loop shape and the other thirty-four(34) lines of the side wall patterns 14b form the closed loop shapesbetween the side wall patterns 14b adjacent to each other.

After that, as shown in FIG. 9B, a space “S” is formed on the cut regionlocated at the end portions of the side wall patterns 14b, between thefirst wiring pattern group 20A, the resist 15 having a hexagonal shapeis formed, the cut region of the side wall patterns 14b is cut by thelithography method, and as shown in FIG. 9C, the wiring patterns 11a,11b similar to those of the fourth embodiment are formed.

(Seventh Embodiment)

FIGS. 10A to 10C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a seventh embodiment. FIG. 10A corresponds to FIG. 1D, FIG.10B corresponds to FIG. 2B, and FIG. 10C corresponds to FIG. 1H.Further, drawings corresponding to FIGS. 1A to 1C are omitted.

As shown in FIG. 10A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the seventh embodiment, twenty-six(26) lines of the side wall patterns 14b located at the side close tothe first wiring pattern group 20A are connected each other so as toform a closed loop shape between two side wall patterns 14b, startingfrom the two side wall patterns 14b closest to the first wiring patterngroups 20A. Further, the ten (10) lines of the side wall patterns 14blocated interiorly form the closed loop shapes between the side wallpatterns 14b adjacent to each other.

After that, as shown in FIG. 10B, a space “S” is formed on the cutregion located at the end portion of the side wall patterns 14b, betweenthe first wiring pattern group 20A, the resist 15 having a hexagonalshape is formed, the cut region of the side wall patterns 14b is cut bythe lithography method, and as shown in FIG. 10C, the wiring patterns11a, 11b similar to those of the fourth embodiment are formed.

(Eighth Embodiment)

FIGS. 11A to 11C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the eighth embodiment. FIG. 11A corresponds to FIG. 1D,FIG. 11B corresponds to FIG. 2B, and FIG. 11C corresponds to FIG. 1H.Further, drawings corresponding to FIGS. 1A to 1C are omitted.

As shown in FIG. 11A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the eighth embodiment, the side wallpatterns 14b are connected each other so as to form a closed loop shapebetween two side wall patterns 14b, starting from the side wall patterns14b closest to the first wiring pattern groups 20A.

After that, as shown in FIG. 11B, a space “S” is formed on the cutregion located at the end portions of the side wall patterns 14b,between the first wiring pattern group 20A, the resist 15 having ahexagonal shape is formed, the cut region of the side wall patterns 14bis cut by the lithography method, and as shown in FIG. 11C, the wiringpatterns 11a, 11b are formed.

According to the fourth to eighth embodiments, even if the side wallpatterns formed by a line and space have an arrangement pitch less thanthe resolution limit “W” in lithography method, the closed loop cut ofthe side wall patterns can be carried out.

Next, the ninth to the thirteenth embodiments where the semiconductordevice of the first embodiment is applied to a wiring by a line andspace will be explained. The ninth to the thirteenth embodiments show acase that the wiring patterns 11a, 11b constituting each of wiringpattern groups 20A, 20B include thirty-six (36) lines of 20 nm in linewidth respectively.

(Ninth Embodiment)

FIGS. 12A to 12C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the ninth embodiment. FIG. 12A corresponds to FIG. 1D, FIG.12B corresponds to FIG. 2B, and FIG. 12C corresponds to FIG. 1H.Further, drawings corresponding to FIGS. 1A to 1C are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 11A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the ninth embodiment, the side wallpatterns 14b are connected each other so as to form a closed loop shapebetween the side wall patterns 14b, starting from the side wall patterns14b closest to the first wiring pattern groups 20A, and to provide asymmetrical appearance.

After that, as shown in FIG. 12B, a space “S” is formed on the cutregion located at the end portions of the side wall patterns 14b,between the first wiring pattern group 20A, the resist 15 having anoctagon shape is formed, the cut region of the side wall patterns 14b iscut by the lithography method, and as shown in FIG. 12C, the wiringpatterns 11a, 11b are formed.

(Tenth Embodiment)

FIGS. 13A to 13C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the tenth embodiment. FIG. 13A corresponds to FIG. 1D, FIG.13B corresponds to FIG. 2B, and FIG. 13C corresponds to FIG. 1H.Further, drawings corresponding to FIGS. 1A to 1C are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 13A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the tenth embodiment, sixteen (16)lines of the side wall patterns 14b located at the sides close to thefirst wiring pattern groups 20A are connected each other at theright-and-left end portions (not shown) so as to form the closed loopshapes between the side wall patterns 14b close to the first wiringpattern groups 20A. Further, ten (10) lines of the side wall patterns14b located interiorly are connected each other so as to form the closedloop shape between the side wall patterns 14b, starting from the sidewall patterns 14b closest to the first wiring pattern groups 20A, and soas to provide a symmetrical appearance. Further, ten (10) lines of theside wall patterns 14b located further interiorly form the closed loopshapes between the side wall patterns 14b adjacent to each other, andprovide a symmetrical appearance.

After that, as shown in FIG. 13B, a space “S” is formed on the cutregion located at the end portions of the side wall patterns 14b,between the first wiring pattern group 20A, the resist 15 having anoctagon shape is formed, the cut region of the side wall patterns 14b iscut by the lithography method, and as shown in FIG. 13C, the wiringpatterns 11a, 11b are formed.

(Eleventh Embodiment)

FIGS. 14A to 14C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the eleventh embodiment. FIG. 14A corresponds to FIG. 1D,FIG. 14B corresponds to FIG. 2B, and FIG. 14C corresponds to FIG. 1H.Further, drawings corresponding to FIGS. 1A to 1C are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 14A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the eleventh embodiment, two (2)lines of the side wall patterns 14b located at the sides closest to thefirst wiring pattern groups 20A are connected each other at theright-and-left end portions (not shown) so as to form a loop shapebetween the two side wall patterns 14b, and the other side wall patterns14b located interiorly form the loop shapes between the side wallpatterns 14b adjacent to each other, and provide a symmetricalappearance.

After that, as shown in FIG. 14B, a space “S” is formed on the cutregion located at the end portions of the side wall patterns 14b,between the first wiring pattern group 20A, the resist 15 having anoctagon shape is formed, the cut region of the side wall patterns 14b iscut by the lithography method, and as shown in FIG. 14C, the wiringpatterns 11a, 11b are formed.

(Twelfth Embodiment)

FIGS. 15A to 15C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the twelfth embodiment. FIG. 15A corresponds to FIG. 1D,FIG. 15B corresponds to FIG. 2B, and FIG. 15C corresponds to FIG. 1H.Further, drawings corresponding to FIGS. 1A to 1C are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 15A, the side wall patterns 14b constituting the secondwiring pattern group 20B of the twelfth embodiment have a structure thata side wall pattern 14b having a hexagonal shape in the center portionis added to the side wall patterns 14b of the eleventh embodiment, andthe other parts are formed similarly to those of the eleventhembodiment.

After that, as shown in FIG. 15B, a space “S” is formed on the cutregion located at the end portions of the side wall patterns 14b,between the first wiring pattern group 20A, the resist 15 having anoctagon shape is formed, the cut region of the side wall patterns 14b iscut by the lithography method, and as shown in FIG. 15C, the wiringpatterns 11a, 11b similar to those of the eighth embodiment are formed.

(Thirteenth Embodiment)

FIGS. 16A to 16C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the thirteenth embodiment. FIG. 16A corresponds to FIG. 1D,FIG. 16B corresponds to FIG. 2B, and FIG. 16C corresponds to FIG. 1H.Further, drawings corresponding to FIGS. 1A to 1C are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 16A, in the side wall patterns 14b constituting thesecond wiring pattern group 20B of the thirteenth embodiment, two (2)lines of the side wall patterns 14b located at the sides closest to thefirst wiring pattern groups 20A are connected each other at theright-and-left end portions (not shown) so as to form a loop shapebetween the two side wall patterns 14b. Further, twenty-four (24) linesof the side wall patterns 14b located interiorly form the loop shapesbetween the side wall patterns 14b, from the parts located externally tothe parts located internally in order, and provide a symmetricalappearance. Ten (10) lines of the side wall patterns 14b located furtherinteriorly form the loop shapes between the side wall patterns 14badjacent to each other, and provide a symmetrical appearance.

After that, as shown in FIG. 16B, a space “S” is formed on the cutregion located at the end portions of the side wall patterns 14b,between the first wiring pattern group 20A, the resist 15 having anoctagon shape is formed, the cut region of the side wall patterns 14b iscut by the lithography method, and as shown in FIG. 16C, the wiringpatterns 11a, 11b similar to those of the seventh embodiment are formed.

Next, the fourteenth to the seventeenth embodiments where thesemiconductor device of the second embodiment is applied to aphase-change memory will be explained. The fourteenth to the seventeenthembodiments show a case that the wiring patterns 11a, 11b constitutingeach of wiring pattern groups 20A, 20B include thirty-three (33) linesof 20 nm in line width respectively.

FIGS. 17A to 17H are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the fourteenth embodiment. FIGS. 17A to 17D correspond toFIGS. 3A to 3D, FIG. 17E corresponds to FIG. 3G, and FIG. 17Fcorresponds to FIG. 3H. FIG. 17G corresponds to FIG. 4B, and FIG. 17Hcorresponds to FIG. 4C.

Similarly to the second embodiment, as shown in FIG. 17A, after a maskmaterial is formed on a foundation layer, core patterns 13a, 13b areformed on the mask material. The core patterns 13b constituting thesecond wiring pattern group 20B are connected each other so as to form aclosed loop shape between two core patterns 13b, starting from the twoside wall patterns 14b closest to the first wiring pattern groups 20A.

Next, as shown in FIG. 17B, a slimming treatment of the core patterns13a, 13b is carried out, and as shown in FIG. 17C, side wall patterns14a, 14b are formed on the side surfaces of the core patterns 13a, 13bafter the slimming treatment, and as shown in FIG. 17D, the corepatterns 13a, 13b are eliminate by an etching so as to leave the sidewall patterns 14a, 14b.

Next, as shown in FIG. 17E, the mask material is eliminated by anetching and by using the side wall patterns 14a, 14b as a mask so as toform mask patterns, and the side wall patterns 14a, 14b are eliminated.

Next, as shown in FIG. 17E, the wiring material 11 is filled in theperipheral of the mask patterns 12a, 12b.

Next, as shown in FIG. 17F, the mask patterns 12a, 12b are eliminated soas to form wiring patterns 11a, 11b. The wiring patterns 11a, 11b formclosed loop shapes. Wide patterns 11e are formed between the wiringpattern groups 20A.

Next, as shown in FIG. 17G, a space “S” is formed on the cut regionlocated at the end portions of the wiring patterns 11b, between thefirst wiring pattern group 20A, the resist 15 having a hexagonal shapeis formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 17H, the wiring patterns 11a,11b are formed.

(Fifteenth Embodiment)

FIGS. 18A to 18C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a fifteenth embodiment. FIG. 18A corresponds to FIG. 3H.FIG. 18B corresponds to FIG. 4B, and FIG. 18C corresponds to FIG. 4C.Further, drawings corresponding to FIGS. 3A to 3G are omitted.

As shown in FIG. 18A, the wiring patterns 11b constituting the secondwiring pattern group 20B of the fifteenth embodiment are connected eachother on alternate lines so as to form closed loop shapes between thewiring patterns 11b, further, the wiring patterns 11a of the wiringpattern groups 20A closest to the first wiring pattern group 20B arealso connected each other so as to form a closed loop shape between thewiring patterns 11a.

After that, as shown in FIG. 18B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having a hexagonalshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 18C, the wiring patterns 11a,11b are formed.

(Sixteenth Embodiment)

FIGS. 19A to 19C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the sixteenth embodiment. FIG. 19A corresponds to FIG. 3H.FIG. 19B corresponds to FIG. 4B, and FIG. 19C corresponds to FIG. 4C.Further, drawings corresponding to FIGS. 3A to 3G are omitted.

As shown in FIG. 19A, the wiring patterns 11b constituting the secondwiring pattern group 20B of the sixteenth embodiment are connected eachother on alternate lines so as to form closed loop shapes between thewiring patterns 11b, further, the wiring patterns 11a of the wiringpattern groups 20A closest to the first wiring pattern group 20B arealso connected each other so as to form a closed loop shape between thewiring patterns 11a.

After that, as shown in FIG. 19B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having a hexagonalshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 19C, the wiring patterns 11a,11b similar to those of the twelfth embodiment are formed.

FIGS. 20A to 20C are main part plan views schematically showing anexample of a fabrication process according to a seventeenth embodiment

(Seventeenth Embodiment)

FIGS. 20A to 20C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the seventeenth embodiment. FIG. 20A corresponds to FIG.3H. FIG. 20B corresponds to FIG. 4B, and FIG. 20C corresponds to FIG.4C. Further, drawings corresponding to FIGS. 3A to 3G are omitted.

As shown in FIG. 20A, in the wiring patterns 11b constituting the secondwiring pattern group 20B of the seventeenth embodiment, twenty-four (24)lines of the wiring patterns 11b located at the side close to the firstwiring pattern group 20A are connected each other so as to form a closedloop shape between two wiring patterns 11b, starting from the two wiringpatterns 11b closest to the first wiring pattern groups 20A. Further,nine (9) lines of the wiring patterns 11b located interiorly areconnected alternatively to the wiring patterns 11b having a closed loopshape and located most interiorly. Furthermore, the wiring patterns 11aof the wiring pattern groups 20A closest to the first wiring patterngroup 20B are also connected each other so as to form a closed loopshape between the wiring patterns 11a.

After that, as shown in FIG. 20B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having a hexagonalshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 20C, the wiring patterns 11a,11b are formed.

Next, the eighteenth to twenty-second the embodiments where thesemiconductor device of the second embodiment is applied to a wiring bya line and space will be explained. The eighteenth to twenty-secondembodiments show a case that the wiring patterns 11a, 11b constitutingeach of wiring pattern groups 20A, 20B include thirty-six (36) lines of20 nm in line width respectively.

(Eighteenth Embodiment)

FIGS. 21A to 21C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the eighteenth embodiment. FIG. 21A corresponds to FIG. 4A,FIG. 21B corresponds to FIG. 4B, and FIG. 21C corresponds to FIG. 4C.Further, drawings corresponding to FIGS. 3A to 3G are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 21A, in the wiring patterns 11b constituting the secondwiring pattern group 20B of the eighteenth embodiment, thirty-two (32)lines of the wiring patterns 11b except for the lines centrally locatedare connected each other so as to form a closed loop shape between thewiring patterns 11b, starting from the wiring patterns 11b closest tothe first wiring pattern groups 20A, and to provide a symmetricalappearance.

After that, as shown in FIG. 21B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having an octagonshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 21C, the wiring patterns 11a,11b are formed.

(Nineteenth Embodiment)

FIGS. 22A to 22C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the nineteenth embodiment. FIG. 22A corresponds to FIG. 4A,FIG. 22B corresponds to FIG. 4B, and FIG. 22C corresponds to FIG. 4C.Further, drawings corresponding to FIGS. 3A to 3G are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 22A, the wiring patterns 11b constituting the secondwiring pattern group 20B of the nineteenth embodiment are alternativelyconnected to the wide patterns 11e formed in the center portion so as toform the closed loop shapes and to provide a symmetrical appearance.Further, the wiring patterns 11a of the first wiring pattern groups 20Aclosest to the second wiring pattern group 20B include a part (atriangular shape) having a wide line width formed in the vicinity of thecut region where the closed loop cut is carried out.

After that, as shown in FIG. 22B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having a hexagonalshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 22C, the wiring patterns 11a,11b similar to those of the twelfth embodiment are formed.

(Twentieth Embodiment)

FIGS. 23A to 24C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the twentieth embodiment. FIG. 23A corresponds to FIG. 4A,FIG. 23B corresponds to FIG. 4B, and FIG. 23C corresponds to FIG. 4C.Further, drawings corresponding to FIGS. 3A to 3G are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 23A, the wiring patterns 11b constituting the secondwiring pattern group 20B of the twentieth embodiment are alternativelyconnected to circular patterns formed in the periphery of the widepatterns 11e centrally located so as to form the closed loop shapes andto provide a symmetrical appearance. Further, the wiring patterns 11a ofthe first wiring pattern groups 20A closest to the second wiring patterngroup 20B include a part (a triangular shape) having a wide line widthformed in the vicinity of the cut region where the closed loop cut iscarried out.

After that, as shown in FIG. 23B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having a hexagonalshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 23C, the wiring patterns 11a,11b are formed.

(Twenty-First Embodiment)

FIGS. 24A to 24C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to a twenty-first embodiment. FIG. 24A corresponds to FIG. 4A,FIG. 24B corresponds to FIG. 4B, and FIG. 24C corresponds to FIG. 4C.Further, drawings corresponding to FIGS. 3A to 3G are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 21A, in the wiring patterns 11b constituting the secondwiring pattern group 20B of the twenty-first embodiment, twenty-six (26)lines of the wiring patterns 11b located at the side close to the firstwiring pattern group 20A are connected each other so as to form a closedloop shape between two wiring patterns 11b, starting from the two wiringpatterns 11b closest to the first wiring pattern groups 20A, and so asto provide a symmetrical appearance. Further, the ten (10) lines of thewiring patterns 11b located interiorly are alternatively connected tothe wiring patterns 11b having a closed loop shape and locatedinteriorly, and provide a symmetrical appearance. Further, the wiringpatterns 11a of the first wiring pattern groups 20A closest to thesecond wiring pattern group 20B include a part (a triangular shape)having a wide line width formed in the vicinity of the cut region wherethe closed loop cut is carried out.

After that, as shown in FIG. 24B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having an octagonshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 24C, the wiring patterns 11a,11b are formed.

(Twenty-Second Embodiment)

FIGS. 25A to 25C are main part plan views schematically showing each ofupper wiring layers used in an example of a fabrication processaccording to the twenty-second embodiment. FIG. 25A corresponds to FIG.4A, FIG. 25B corresponds to FIG. 4B, and FIG. 25C corresponds to FIG.4C. Further, drawings corresponding to FIGS. 3A to 3G are omitted.Furthermore, the embodiment shows a case that the second wiring patterngroups 20B exist in the right-and-left sides.

As shown in FIG. 25A, in the wiring patterns 11b constituting the secondwiring pattern group 20B of the twenty-second embodiment, twenty-two(22) lines of the wiring patterns 11b located at the side close to thefirst wiring pattern group 20A form the closed loop shapes between thewiring patterns 11b in the right-and-left end portions (not shown)Further, the four (4) lines of the wiring patterns 11b locatedinteriorly are connected each other so as to form a closed loop shapebetween the wiring patterns 11b, starting from the wiring patterns 11bclosest to the first wiring pattern groups 20A, and so as to provide asymmetrical appearance. Further, nine (9) lines of the wiring patterns11b located further interiorly are alternatively connected to the closedloop shapes located interiorly so as to provide a symmetricalappearance. Further, the wiring patterns 11a of the first wiring patterngroups 20A closest to the second wiring pattern group 20B include a part(a triangular shape) having a wide line width formed in the vicinity ofthe cut region where the closed loop cut is carried out.

After that, as shown in FIG. 25B, a space “S” is formed on the cutregion located at the end portions of the wiring patterns 11b, betweenthe first wiring pattern group 20A, the resist 15 having an octagonshape is formed, the cut region of the wiring patterns 11b is cut by thelithography method, and as shown in FIG. 25C, the wiring patterns 11a,11b are formed.

Further, it should be noted that the present invention is not intendedto be limited to the above-mentioned embodiments, and the various kindsof changes thereof can be implemented by those skilled in the artwithout departing from the gist of the invention.

What is claimed is:
 1. A method of fabricating a semiconductor device,comprising: forming a first pattern and a second pattern, the firstpattern having linear parts of a constant line width, and the secondpattern having parallel parts parallel to the linear parts and nonlinearparts not parallel to the linear parts, wherein: the parallel parts areat a first distance away from the linear parts, the parallel parts andthe nonparallel parts are connected to each other at joining points, thenonparallel parts bend from the joining points in a direction away fromthe linear parts, and the second pattern is formed in a closed loopshape; and forming a resist over the nonparallel parts, a point on theresist, which is closest to the linear parts, being at a second distanceaway from the linear parts, the second distance being larger than thefirst distance; and carrying out a closed loop cut at a region coveredby the resist.
 2. The method of fabricating a semiconductor deviceaccording to claim 1, wherein: the second pattern is formed such thatthe nonparallel parts are connected to form the closed loop shape. 3.The method of fabricating a semiconductor device according to claim 1,wherein: the first pattern is formed in a closed loop shape, and formingthe first pattern and the second pattern comprises: forming corepatterns on a foundation layer, forming side wall patterns on sidesurfaces of the core patterns, and removing the core patterns, leavingthe side wall patterns on the foundation layer, wherein the firstpattern includes a first one of the side wall patterns and the secondpattern includes a second one of the side wall patterns.
 4. The methodof fabricating a semiconductor device according to claim 3, wherein: theclosed loop cut is carried out to the second pattern including thesecond one of the side wall patterns.
 5. The method of fabricating asemiconductor device according to claim 3, wherein: the closed loop cutis carried out to a wiring material filled in grooves having a closedloop shape, the grooves being formed by etching a processed film formedin the foundation layer or formed between the foundation layer and thesecond pattern by using the second pattern including the side wallpatterns as a mask.
 6. A method of fabricating a semiconductor device,comprising: forming a first pattern group including a plurality of firstpatterns arranged at a predetermined pitch and a second pattern groupincluding a plurality of second patterns arranged at the predeterminedpitch, one of the second patterns closest to the first pattern grouphaving parallel parts parallel to the first patterns and nonparallelparts not parallel to the first patterns, wherein: the parallel partsare at a first distance away from a one of the first patterns which isclosest to the second pattern group, the parallel parts and thenonparallel parts are connected to each other at joining points, thenonparallel parts bend from the joining points in a direction away fromthe first patterns, and the second pattern is formed in a closed loopshape; forming a resist over the nonparallel parts, a point on theresist, which is closest to the first pattern group, being at a seconddistance away from the one of the first patterns closest to the secondpattern group, the second distance being larger than the first distance;and carrying out a closed loop cut at a region covered by the resist. 7.The method of fabricating a semiconductor device according to claim 6,wherein: the first patterns have linear parts of a constant line widthand are formed in closed loop shapes, and forming the first patterngroup and the second pattern group comprises: forming core patterns on afoundation layer, forming side wall patterns on side surfaces of thecore patterns, and removing the core patterns, leaving the side wallpatterns on the foundation layer, wherein the first patterns includefirst ones of the side wall patterns and the second patterns includesecond ones of the side wall patterns.
 8. The method of fabricating asemiconductor device according to claim 7, wherein: the closed loop cutis carried out to a wiring material filled in grooves having a closedloop shape, the grooves being formed by etching a processed film formedin the foundation layer or formed between the foundation layer and thesecond pattern by using the second pattern including the side wallpatterns as a mask.
 9. The method of fabricating a semiconductor deviceaccording to claim 6, wherein: the first pattern group and secondpattern group are shifted in opposite directions along a line parallelto a direction in which the first patterns and the second patternsextend.
 10. The method of fabricating a semiconductor device accordingto claim 6, wherein the first pattern group and the second pattern groupconstitute a lower wiring layer, and the method further comprises:repeating the steps of claim 6 to form a third pattern group including aplurality of third patterns and a fourth pattern group including aplurality of fourth patterns, the third and fourth pattern groups beingformed over the first and the second pattern groups, wherein: the thirdpattern group is formed similar to the first pattern group, the fourthpattern group is formed similar to the second pattern group, the thirdpatterns and the fourth patterns extend in a direction perpendicular tothe first patterns and the second patterns, and the third pattern groupand the fourth pattern group constitute an upper wiring layer.
 11. Themethod of fabricating a semiconductor device according to claim 6,wherein: after the closed loop cut is carried out, forming contactfringes.
 12. A method of fabricating a semiconductor device including awiring pattern, comprising: forming an insulating layer above asemiconductor substrate; forming a first pattern part, a second patternpart, and a third pattern part on the insulating layer, wherein: thefirst pattern part linearly extends in an extension direction on theinsulating layer, the second pattern part: is adjacent and parallel tothe first pattern part, and is at a first distance away from the firstpattern part, and the third pattern part: is connected to the secondpattern part continuously, and is adjacent and nonparallel to the firstpattern part, and a distance between the first pattern part and thethird pattern part gradually increases with a distance from the secondpattern part along the extension direction; forming a masking layerabove the third pattern part, a point on an edge of the masking layer,which is closest to the first pattern part, being at a second distanceaway from the first pattern part, the second distance being larger thanthe first distance; and etching the insulating layer using the first,second, and third pattern parts as a mask.
 13. The method according toclaim 12, wherein the semiconductor device is a semiconductor memorydevice.
 14. The method according to claim 12, further comprising:forming, after etching the insulating layer, the wiring pattern in asame layer as the insulating layer.
 15. The method according to claim14, wherein the wiring pattern includes at least one of Cu, Al, or W.